The power and capacity of computing components such as microprocessors and memory circuits has been increasing for the last 50 years, as the size of the functional units, such as transistors, has been decreasing. This trend is now reaching a limit, however, as it is difficult to make the current functional units (such as MOSFETs) any smaller without affecting their operation.
The technology employed to manufacture conventional silicon integrated circuits is today well established. Current microprocessors feature several hundreds of millions of transistors which are manufactured in high throughput lines.
Developments are ongoing to implement new types of advanced processing apparatuses that can implement powerful computations exploiting the rules of quantum mechanics. Such advanced processing apparatuses promise computational capacities well beyond current devices for a specific range of algorithms. Approaches to the realisation of devices for implementing quantum bits (qubits), the basic computational unit of a quantum processor, have been explored with different levels of success. A workable quantum processor needs to be able to perform two-qubit operations with low-error thresholds and be scalable. For example, semiconductor based qubits have been developed and described in a number of earlier patent publications, including U.S. Pat. No. 6,472,681 (Kane), U.S. Pat. No. 6,369,404 (Kane). The operation of these qubits is based on the exploitation of the quantum effects of a single dopant atom in a silicon crystalline lattice and the interaction between qubits is mediated by electron exchange coupling.
One of the problems related to this model is that the exchange interaction between electrons decays exponentially with donor separation and is highly dependent on the precise placement of the donors within a single lattice site, due to the oscillatory profile of the electron wave-function. The successful implementation of this architecture requires positioning of donors, separated by only 15 nm, with sub-nm precision. Such a level of precision makes the fabrication of the architecture very challenging, as discussed for example in U.S. Pat. No. 7,547,648 (Ruess et al.).
It has also been proposed to encode quantum information using the spin states of semiconductor quantum dots (Loss and DiVincenzo (Loss, DiVincenzo, DP quantum computation with quantum dots. Phys Rev. A56, 120; 1998).). This proposal primarily envisaged the use of quantum dots formed using electrostatic gates on a GaAs/AlGaAs heterostructure. However, the limited coherence time and the associated fidelity of the quantum state in these systems represent a significant hurdle to application of quantum dots in a quantum processor. Experimental work has been done in GaAs/AlGaAs on quantum dot qubits, but to realise large-scale arrays of such structures will require new manufacturing process technologies to be developed. More importantly, these materials suffer from problems with fidelity and dephasing time due to the presence of nuclear spins that are inherent to the GaAs crystal lattice.
Superconducting qubits have recently achieved low-error performance and a promising scalability. These qubits however have a macroscopic size (hundreds of micrometres scale) which prevents architectures from being fabricated with a large number of qubits within a small chip size. The large size, combined with the operation a GHz frequencies, can pose challenges in controlling the electromagnetic modes of a large number of qubits hosted in a cavity wider than the wavelength of the electromagnetic fields.